The present invention relates to a DRAM (dynamic random access memory) refresh circuit, and more particularly, to a DRAM refresh circuit suitable for improving memory access characteristics by efficiently performing the DRAM's memory access and refresh operations in a DRAM controller.
Generally, a DRAM is manufactured by using MOS technology, and includes memory cells having a large capacitance, low power consumption, but limited operation speed.
An SRAM, on the other hand, has a fast information processing speed and does not need refresh. The SRAM, however, is more expensive than the DRAM, and, therefore, DRAMs are more widely used than SRAMs.
Unlike the SRAM in which information is stored in a flipflop, the DRAM memory cell capacitor stores an amount of charge indicative of a "1" or a "0." After a given amount of time, however, this charge can leak away, thereby, erasing information stored in the DRAM cell. Accordingly, the DRAM's memory cells must be periodically recharged or refreshed at least every 2-10 ns, otherwise, data is lost.
A conventional DRAM refresh circuit will now be described with reference to FIGS. 1 and 2, which illustrate a block diagram of a conventional DRAM refresh circuit (FIG. 1), and timing diagram (FIG. 2) relative to the circuit shown in FIG. 1.
The DRAM refresh circuit includes a memory read controller 1 for receiving the CPU's program control signal and controlling the DRAM's read operation. A memory write controller 2 and refresh controller 3 are also coupled to the CPU for controlling the DRAM's write and refresh operations, respectively. OR gate 4 performs a logical operation on the output signals of memory read controller 1 and memory write controller 2 to output a write/read normal mode enable signal. Lastly, a memory control signal generator 5 receives the output signal from OR gate 4 and the refresh enable signal from refresh controller 3 and outputs RASI (row address strobe) and CASI (column address strobe) signals in response thereto.
FIG. 2 is a DRAM-refresh mode timing diagram illustrating operation of the circuit shown in FIG. 1. In FIG. 2, the operation time is divided into frames, each of which includes a plurality of slots. A single predetermined slot in each frame is designated for the refresh mode.
In order to write data into the DRAM, the DRAM is placed in a write operation mode. In which case, the CPU transmits a write signal to memory write controller 2, which supplies the write signal to control signal generator 5 via OR gate 4. Memory control signal generator 5, in turn, produces normal mode RASI and CASI signals.
After the data write, the CPU performs the refresh operation in order to prevent data loss in the DRAM. In order to read data into the controller 3, proper data must be accessed. Here, the CPU must appropriately allocate time to read data and time to refresh. As shown in FIG. 2, during the period from the first slot to the second to last slot in each frame, the CPU uses memory read controller 1 to produce the RASI and CASI signals in order to read data in the normal mode. In the last slot of each frame, the CPU uses refresh controller 3 to produce the refresh enable signal, in response to which control signal generator 5 outputs a CASI signal before a RASI signal.
In the conventional DRAM refresh circuit, the CPU must allot both the memory access and refresh functions. For this reason, data is not read during the refresh mode. Accordingly, data processing is not efficiently performed when a significant amount of data must be processed.